1. Technical Field
The present invention relates to a magnetic disk drive, and more particularly a serial interface read-back drive circuit for reading back the data stored in the various registers within a read/write channel circuit.
2. Related Art
Recently, data storing and retrieving techniques have been rapidly and greatly improved so that high-capacity and high-speed storage devices, like hard disk drives, are manufactured and are widely employed as auxiliary storage devices for computer systems.
In magnetic disk drives, a read/write channel circuit detects and decodes data pulses from read signals transmitted by a preamplifier coupled to heads so as to apply them to the DDC (disk data controller), and conversely the read/write channel circuit decodes write data from the DDC to apply to the preamplifier. When retrieving data, the preamplifier amplifies signals picked up by heads from disks (recording medium) so as to apply them to the read/write channel circuit and, when recording data, the preamplifier selects a head in response to the instruction of the DDC so as to record the encoded write data received from the read/write channel circuit on the corresponding disk.
The read/write channel circuit controls the internal constituent circuits through an internal built-in serial port under the control of a central processing unit(CPU). Various states of the internal constituent circuit blocks of a read/write channel circuit are transferred through the serial port to the CPU. Namely, the above serial port is a bidirectional port which serially interfaces between the read/write channel circuit and the CPU.
By way of example, a read/write channel circuit includes an ENcoder/DECoder(ENDEC) which decodes recording data and encodes synchronous reading data, a pulse and servo detector which detects the amplitude of a burst to generate position error signals and detects peak values of amplitudes of the preamplified signals, and a data separator which separates read data, synchronized with specific clocks, from data pulses generated by the pulse and servo detector. The read/write channel circuit further includes an automatic gain control (AGC) circuit, a programmable filter, a hysteresis qualifier, etc. Each of the internal constituent circuits has respective registers for storing information used for operational control of the corresponding circuit.
The built-in serial port in the read/write channel circuit has n number of serial port registers (hereinafter referred to as "state control registers"). For example, n number of state control registers are respective registers for setting power-down, data mode cut-off, servo mode cut-off, filter boost, data threshold value, servo threshold value, data restoring, and AGC level, etc. Each of the registers has a specific control value for setting its corresponding function.
The CPU applies the serial port control signals, i.e. SDEN, SDATA and SCLK, to the above serial port, where SDEN is a data transmission enabling signal, SDATA is serial data of the CPU, and SCLK is a serial clock signal. The SDATA carries the address for selecting the specified state control register of the serial port and the data for reading (or writing) the control state of the register selected by the above address. The address of the serial data includes the read/write selection bits for controlling the data reading and/or writing selections.
When the serial port control signal is applied, the CPU accesses the state control register according to the address in the serial data SDATA and reads (or writes) the control state from (or to) the register accessed according to the data in the SDATA. The read or write selection is performed according to the binary logical state of the read/write selection bit in the address. If the control state is written, the serial port loads the above control state on the corresponding circuit of the read/write channel circuit. If the control state is read, the serial port loads the current control state of the accessed state control register on the serial data SDATA to transfer it to the CPU.
Since the read/write channel circuit is packed in a single chip which is specially designed by the manufacturer, it is natural that the bit numbers of the serial ports for interfacing between the read/write channel circuit and the CPU be different, depending on manufacturer. The bit numbers of the serial ports are, for example, 16 bits, 18 bits and 8 bits, which indicates a variety of serial port uses. FIG. 4 illustrates the serial port control signal in case of the serial port of 16 bits.
In order to serially interface between the conventional read/write channel circuits of various standards and the CPU according to the prior art, the related control designs of the CPU or DSP (digital signal processor) should be modified by adapting to the bit number of the serial port of the read/write channel circuit. Accordingly, to remove such inconveniences, it is desirable to devise a serial interface circuit which can be adapted to the read/write channel circuits of various standards.
For reference, a serial interface circuit for adaptively supporting the serial interface of the read/write channel circuits of various standards is disclosed in the Korean Patent Application No. 96-41480 under the title of "Serial Interface Circuit".
Although the above serial interface circuit disclosed in the Korean Patent Application No. 96-41480 supports adaptively the serial interface of the read/write channel circuits of various standards, the CPU cannot access the serial port register and read the contents thereof. In other words, the CPU supplies the state control registers with the serial port control signals adaptive to various interface bit numbers by means of the newly invented serial interface circuit, but cannot read the control state set in the state control register. Particularly in the test mode, where various information of the read/write channel circuit are loaded on the specific serial port, the CPU cannot access the above serial port.
The following U.S. patents disclose other arrangements which are representative of the prior art relative to the invention disclosed herein, but such arrangements are also burdened by the disadvantages discussed above: U.S. Pat. No. 5,671,252 to Kovacs et al., entitled Sampled Data Read Channel Utilizing Charge-Coupled Devices, U.S. Pat. No. 5,434,717 to Yoshinaga et al., entitled Read And/Or Write Integrated Circuit Having An Operation Timing Adjusting Circuit And Constant Current Elements, U.S. Pat. No. 5,424,881 to Behrens et al., entitled Synchronous Read Channel, U.S. Pat. No. 5,257,248 to Ogasawara, entitled Information Recording Apparatus Capable Of Efficiently Verifying Recording Information, U.S. Pat. No. 5,121,262 to Squires et al., entitled Disk Drive System Employing Adaptive Read/Write Channel Controls And Method Of Using Same, U.S. Pat. No. 5,084,789 to Kamo et al., entitled Parallel Transfer Type Disk System, U.S. Pat. No. 4,875,112 to Dost et al., entitled Compound Pulse Dimming Circuitry For Conditioning Readback Signals, U.S. Pat. No. 4,327,383 to Holt, entitled Read Circuit For A Floppy Disk Drive, and U.S. Pat. No. 4,244,008 to Holt, entitled Read Back Compensation Circuit For A Magnetic Recording Device.